1. Field of the Invention
The present invention relates to a semiconductor device. More particularly, the present invention relates to a compound semiconductor device which requires heat dissipation.
2. Description of the Related Art
Conventionally, a compound semiconductor device which requires heat dissipation is known in which a bump is formed on an electrode provided on a semiconductor device formed on a semiconductor substrate. The compound semiconductor device is mounted on a mounting substrate by connecting the bump with an electrode formed on the mounting substrate in such a manner that the upper surface of the bump faces the mounting substrate. Such a mounting is referred to as flip chip bonding which allows for high density mounting of the device and is considered to be an effective way of mounting an LSI (large scale integrated circuit). LSIs have been increasing the number of input terminals and reducing in size at remarkable rate.
In the case where flip chip bonding is used for a power transistor, the bump serves not only as the electrode but also as a heat dissipation path for dissipating heat generated in the device. Particularly, in a hetrojunction bipolar transistor device (hereinafter, simply referred to as an "HBT device"), heat generation density tends to become substantially higher when operated with high current density. Thus, in order to properly operate the HBT device, the heat generated inside the device needs to be dissipated effectively. The above-described flip chip bonding is considered particularly effective for such a requirement.
Technology of using such a bump for heat dissipation is disclosed, for example, in Technical Report of the Institute of Electronics, Information and Communication Engineers, vol. 93, no. 416, "Bump Heat Sink Technology" (1994) by Hasegawa et al., and U.S. Pat. No. 5,373,185 by Sato.
Hereinafter, a conventional compound semiconductor device 300 will be described with reference to FIG. 6. FIG. 6 is a cross-sectional view showing the conventional compound semiconductor device 300. The compound semiconductor device 300 includes a semiconductor multilayer 320, a contact structure 306, an emitter electrode 309, a conductive metal (Ti/Au) layer 312 for plating and a bump 313 provided in this order on a semi-insulating substrate 301 made of GaAs. The bump 313 is electrically connected with the emitter electrode 309 via the conductive metal layer 312 for plating.
The semiconductor multilayer 320 includes a sub-collector layer 302 made of n.sup.+ GaAs (thickness: 500 nm, impurity concentration: 5.0.times.10.sup.18 /cm.sup.3), a collector layer 303 made of n.sup.- GaAs (thickness: 700 nm, impurity concentration: 2.0.times.10.sup.16 /cm.sup.3), a base layer 304 made of p.sup.+ GaAs (thickness: 80 nm, impurity concentration: 2.0.times.10.sup.19 /cm.sup.3 ) and an emitter layer 305 made of n.sup.- AlGaAs (thickness: 120 nm, impurity concentration: 5.0.times.10.sup.17 /cm.sup.3) sequentially provided on a semi-insulating substrate 301, thereby forming an HBT device. The sub-collector layer 302, the base layer 304 and the emitter layer 305 are electrically connected to a collector electrode (AuGe/Ni/Au) 311, a base electrode (Ti/Pt/Au) 310 and an emitter electrode (Ti/Pt/Au) 309, respectively.
The contact structure 306 is formed for providing a contact between the emitter layer 305 and the emitter electrode 309 without alloying. The contact structure 306 includes a first contact layer 306a made of n.sup.+ GaAs (thickness: 50 nm, impurity concentration: 5.0.times.10.sup.18 /cm.sup.3), a second contact layer 306c made of n.sup.+ InGaAs (thickness: 50 nm, impurity concentration: 1.0.times.10.sup.9 /cm.sup.3 or more) and a graded layer 306b made of n.sup.+ InGaAs (thickness: 50 nm, impurity concentration: 1.0.times.10.sup.19 /cm.sup.3). The first contact layer 306a is provided on the emitter layer 305 side, the second contact layer 306c is provided on the emitter electrode 309 side and the graded layer 306b is provided between the first contact layer 306a and the second contact layer 306c.
In the conventional compound semiconductor device 300 shown in FIG. 6, In.sub.x Ga.sub.1-x As (x=0.5) layer is often used as the second contact layer 306c. InGaAs is capable of being doped with an impurity of high concentration and of forming an ohmic electrode having low contact resistance without alloying. Usually, in order to satisfy a strained lattice match and a conduction band match between the second contact layer 306c made of In.sub.0.5 Ga.sub.0.5 As and the first contact layer 306a made of GaAs, the graded layer 306b having an In mole fraction gradually changing from 0 to 0.5 in the thickness direction is formed between the first contact layer 306a and the second contact layer 306c. The In mole fraction of about 0.5 is sufficient for obtaining a satisfactory electrical contact between the first contact layer 306a and the second contact layer 306c. Generally, when the In mole fraction is equal to or more than 0.5, a problem associated with mismatching of lattice constants becomes significant. Therefore, conventionally, an In.sub.x Ga.sub.1-x As layer where x is equal to or more than 0.5 is not intentionally used as the graded layer 306b.
In the above-described conventional compound semiconductor device having bumps, the temperature of the device itself rises due to heat generated upon operation. This heat generation is particularly significant in the case of a power device. As a result, the characteristics and reliability of the power device itself as well as the characteristics and the reliability of devices mounted in the vicinity of the power device are deteriorated. Thus, the conventional device performs poorly as a power device.